ARM..Advanced RISC Machine.
I wasn’t really paying attention to the CMSIS and Startup files earlier…turns out they are quite knowledgeable.
just a basic thing that I think one should know to avoid confusions-
“Large and complex systems are designed by making small parts work independently and then integrate them together..so ADC’s I2C GPIO’s are not the part of processors core(in this case I’m talking aboot Core M3)..they are added by the vendor who fabricated the chip, according to the market need and stuff.
So when we talk about CMSIS, it means the Core and its very basic blocks..like System control block, NVIC, MPU etc.. and documentation about these is provided by ARM not the vendor(like STM or TI etc).
Pixhawk for example..uses NuttX RTOS which provides the environment for other applications to run. It involves a Scheduler.
Where as Bare Metal is like you write some code(without any middleware, *one has to include startup file or a piece of code, to setup the core peripherals and clocks and stuff) and that’s what runs on the microcontroller.”
here are some core blocks in CORE M3
NVIC– Nested Vector Interrupt Controller- Handles Interrupts independently from the core..runs even when the processor is in sleep..handles interrupts from 1-240* and 256 priority levels.
*NVIC has ability to handle 240 interrupts. Don’t mistake it as if your development board is gonna come with 240 external interrupts..compared to 2 external interrupts on an regular arduino.
System Tick is a part of NVIC.
Also at the hardware level NVIC sits right beside the M3 Core which facilitates low latency.
Also priority can be set for different interrupts. Here’s little something in the CORE M3 Technical Reference Manual( Page 5-4)
and here’s something I found in CMSIS Device Peripheral Access layer..names as STM32F10x.h..came along with the device package
NMI has the priority of -2 which is mentioned in Core M3 TR. so I figured, they must have defined it in the CMSIS and also not configurable..turns out vendor can change its priority? also its written RESET has priority of -3 (highest) then it gets even lower to -14..abstraction has its downfall..requires more digging.
Memory Protection Unit– Since there is a lot going on..one can have RTOS on a microcontroller..one requires a unit to decide which process or H/W get access to memory.
System Control Block: This block controls
Debug Interface Port
Trace Port Interface Unit
Also there are ITM and ETM which are Instrumentation Trace Macrocell and Embedded Trace Macrocell.
and if one looks at Core_cm3.c ther are all sorts of functions written in assembly like
PSP is Process Stack Pointer and MSO is Main Stack Pointer..and it is being copied into a Register
bx – branch to “Register which holds the address”
lr is Link Register